1. Field of the Invention
The present invention relates to a semiconductor device with a speed binning test circuit and a test method thereof.
2. Description of the Related Art
In general, semiconductor memory devices such as a Dynamic Random Access Memory (DRAM) and an Application-Specific Integrated Circuit (ASIC) are manufactured by a series of processes. These processes may include a design process, a manufacture process, a chip test process, and a packaging process, before the semiconductor memory devices enter the marketplace. One type of chip test process is referring to as a speed binning test. A speed binning test is one of a series of processes performed after the manufacture process. In high-performance semiconductor memory devices such as those described above, a significant effect of temperature variation during testing is to affect the assessed maximum speed of the device in normal use, known as “speed binning”. In a speed binning test, operation speeds of chips may be measured at a wafer-level, and poor-quality chips or wafers may be sorted out based on the result of measurement.
The operation speeds of semiconductor integrated circuits such as central processing units (CPUs), which are manufactured through an ultra-fine process, rely largely on process variations. Thus, there is a need for monitoring on-chip variations at a wafer level using the speed-binning test, and then predicting the operation features of chips, prior to placing the chips in the marketplace. Accordingly, packaging costs may be reduced. Typically, product costs for packaging a device such as a high-performance CPU is expensive, and the practical utility of working dies is determined primarily by the dies' functional working at a desired speed, rather than the dies' functional working. Therefore, it is more desirable to perform the speed-binning test at the wafer level to sort out poor-quality wafers.
In a conventional speed binning test circuit, a Boundary Scan Register (BSR) installed within the chip may be used to measure turn-around time by using an inverter chain installed around the chip. The turn-around time indicates a delay time duration until an input signal is output. Turn-around time is used for estimating the operation speed of the chip after the packaging process. That is, the range of the chip operation speed may be estimated using tracking plots that are measured based on a correlation between the turn-around time from the inverter chain, and the chip operation speed. The speed-binning test described above is disclosed in U.S. patent application Ser. No. 20020,129,310A1.
A conventional speed binning test method of measuring turn-around time is based on the fact that the operation speed of chip (using the inverter chain and DC characteristics evaluated through a Test Element Group (TEG), for example) depend largely on process variations.
However, as process conditions become more minute and on-chip variations become more serious, it is difficult to accurately predict the operation speed of chip by only using the conventional inverter chain to measure the turn-around time after the packaging process. In other words, the influences of on-chip variations upon circuits at every possible location, e.g., upper, lower, left and right portions, over the chip are represented as a data value, which may be referred to as a ‘total delay value’, in the inverter chain. It is impossible to accurately predict the operation speed based only on the total delay time. For example, it is difficult to determine whether (i) circuits at the every possible location over the chip are affected uniformly by the on-chip variations, or (ii) only a circuit at a particular location is largely affected by the on-chip variations. Thus, it may be difficult to explain why the operation speed of a core circuit becomes slower when the turn-around time for the latter case (ii) equals turn-around time for the former case (i).
Also, in the conventional speed binning test method, influence of on-chip variations is evaluated by manually measuring operation speeds at a number of different locations in the inverter chain (which is installed around the core circuit), using test equipment. The results of these measurements are then stored in a database. However, considerable time is spent on manual evaluation of the operation speed, thus making it difficult to measure the operation speeds of all of chips on a wafer. Accordingly, in the above test method only a few wafers of a lot are selected, and the evaluation is performed on only a few chips of the selected wafers. A distribution of measurement results become wide, as process conditions become even more minute. Thus, these measurement results are not accurate enough to represent the performance of the all chips on a wafer.